This application claims the benefit of Korean Patent Application No. 2001-50165, filed on Aug. 21, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to a driving circuit portion of an LCD device.
2. Discussion of the Related Art
Flat panel display (FPD) devices having small size, lightweight, and low power consumption have been a subject of recent research in the coming of the information age. Among many kinds of FPD devices, LCD devices are widely developed and used because of their excellent characteristics of resolution, color display and display quality.
Generally, LCD devices include an upper substrate and a lower substrate facing each other with liquid crystal molecules interposed therebetween. Each substrate has an electrode on an inner surface thereof. An electric field is generated by applying a voltage to the electrodes, thereby driving the liquid crystal molecules to display images depending on light transmittance.
FIG. 1 is a schematic cross-sectional view of a conventional LCD device.
In FIG. 1, a conventional LCD device has a first region xe2x80x9cAxe2x80x9d where images are displayed, and a second region xe2x80x9cBxe2x80x9d where pads (not shown) connected to driving circuits to apply a signal to the first region xe2x80x9cAxe2x80x9d are disposed. At the first region xe2x80x9cAxe2x80x9d, a gate electrode 11 of conductive material such as metal is formed on a first substrate 10. A gate insulating layer 12 of silicon nitride (SiNx) or silicon oxide (SiO2) is formed on the gate electrode 11. An active layer 13 of amorphous silicon and an ohmic contact layer 14 of impurity-doped amorphous silicon are sequentially formed on the gate insulating layer 12 over the gate electrode 11. Source and drain electrodes 15a and 15b of conductive material such as metal are formed on the ohmic contact layer 14. The source and drain electrodes 15a and 15b compose a thin film transistor (TFT) xe2x80x9cTxe2x80x9d with the gate electrode 11. The gate electrode 11 is connected to a gate line (not shown) and the source electrode 15a is connected to a data line (not shown). The gate line and the data line cross each other and define a pixel region (not shown). A passivation layer 16 of SiNx, SiO2 or organic insulating material is formed on the source and drain electrodes 15a and 15b. The passivation layer 16 has a contact hole 16c exposing the drain electrode 15b. A pixel electrode 17 of transparent conductive material is formed on the passivation layer 16 at the pixel region. The pixel electrode 17 is connected to the drain electrode 15b through the contact hole 16c. 
A second substrate 20 faces and is spaced apart from the first substrate 10. A black matrix 21 corresponding to the TFT xe2x80x9cTxe2x80x9d is formed on an inner surface of the second substrate 20. The black matrix 21 covers portions except the pixel region. A color filter layer 22 is formed on the black matrix 21. The color filter layer 21 has red (R), green (G) and blue (B) colors that are alternately disposed. One color corresponds to one pixel region. A common electrode 23 of transparent conductive material is formed on the color filter layer 22. A liquid crystal layer 30 is interposed between the pixel electrode 17 and the common electrode 23.
The gate insulating layer 12 and the passivation layer 16 of the first substrate 10 and the common electrode 23 of the second substrate 20 are extended to the second region xe2x80x9cBxe2x80x9d. A seal pattern 40 is formed between the passivation layer 16 and the common electrode 23 to supply a gap for injecting liquid crystal material and prevent the injected liquid crystal material from leaking.
The conventional LCD device is formed through fabricating processes including fabricating an array substrate, fabricating a color filter substrate, and assembling a liquid crystal cell. The array substrate has a TFT and a pixel electrode. The color filter substrate has a color filter layer and a common electrode. The liquid crystal cell assembling process includes attaching the array substrate and the color filter substrate, injecting liquid crystal material, sealing and attaching a polarizing plate.
On the other hand, the conventional LCD device further includes a driving unit to drive the TFT. The driving unit includes a driving integrated circuit (IC) to apply a signal to a line of the LCD device. Packaging methods of the driving IC to the LCD device are classified into a chip on glass (COG) type, a tape carrier package (TCP) type and a chip on film (COG) type. In the COG type, since the driving IC is attached onto an array substrate of the LCD device and an output electrode of the driving IC is directly connected to a pad of the array substrate, the structure and fabricating process are simple, and production cost is low.
FIG. 2 is a plan view showing a conventional LCD device of a COG type.
In FIG. 2, the conventional LCD device includes an array substrate 50 and a color filter substrate 60. The array substrate 50 has a larger area than the color filter substrate 60. A seal pattern 70 is formed at a boundary of the color filter substrate 60. Liquid crystal material (not shown) is interposed between the array substrate 50 and the color filter substrate 60 in interior of the seal pattern 70. The interior of the seal pattern 70 is a display region 51 where images are displayed. In the display region 51, gate lines 52 and data lines 53 cross each other and define pixel regions. A TFT (not shown) is disposed near a crossing of a gate line 52 and a data line 53. A gate link line 54 and a data link line 55 are formed at a left edge and a top edge of the array substrate 50, respectively. One end of the gate link line 54 is connected to the gate line 52, and the other end of the gate link line 54 is connected to a gate driving IC 81 packaged on the array substrate 50. One end of the data link line 55 is connected to the data line 53, and the other end of the data link line 55 is connected to a data driving IC 82 packaged on the array substrate 50. The gate driving IC 81 and the data driving IC 82 are connected to an external printed circuit board (PCB) (not shown) through a flexible printed circuit (FPC). Since the PCB includes many devices such as ICs, control signals and data signals are generated to drive an LCD device. Here, the PCB may be divided into a gate portion and a data portion, which are connected to each other through a FPC to interchange a gate signal and a data signal.
As mentioned above, the seal pattern 70 supplies a gap between the substrates 50, 60 for injecting liquid crystal material and prevents the injected liquid crystal material from being leaking. After a specific pattern of heat curable resin is formed on the array substrate 50, the array substrate 50 and the color filter substrate 60 are aligned and attached through hardening the seal patterning 70 under pressure.
As shown in FIG. 1, since a passivation layer 16 (of FIG. 1) is formed on an entire surface of an array substrate 10 (of FIG. 1), the passivation layer 16 (of FIG. 1) also exists beneath the seal pattern 40 (of FIG. 1). Recently, the passivation layer 16 (of FIG. 1) is made of organic insulating material such as benzocyclobutene (BCB) of low dielectric constant. Since adhesion of the seal pattern 40 (of FIG. 1) to the passivation layer 16 (of FIG. 1) of organic insulating material is bad, breakage in the seal pattern 40 (of FIG. 1) may occur. Accordingly, when the passivation layer 16 (of FIG. 1) is formed of organic insulating material, the passivation layer 16 (of FIG. 1) beneath the seal pattern 40 (of FIG. 1) should be eliminated to prevent the problems of a breakage.
FIG. 3A is a schematic magnified plan view of a portion xe2x80x9cCxe2x80x9d of FIG. 2, and FIG. 3B is a schematic cross-sectional view taken along a line IIIbxe2x80x94IIIb of FIG. 3A.
In FIGS. 3A and 3B, a gate insulating layer 56 is formed on an array substrate 50, and a data link line 55 is formed on the gate insulating layer 56. A passivation layer 57 of organic insulating material covers the data link line 55. A seal pattern 70 overlapping the data link line 55 is formed on the passivation layer 57. A color filter substrate 60 including a common electrode 61 is disposed over the seal pattern 70. The color filter substrate 60 is attached to the array substrate 50 by the seal pattern 70. To improve adhesion of the seal pattern 70, the passivation layer 57 has groove 57c between the adjacent data link lines 55 under the seal pattern 70 and through the gate insulating layer 56. Since a contact area of the seal pattern 70 and the passivation layer 57 is reduced, adhesion is improved and breakage of the seal pattern 70 is prevented.
Recently, in a COG type, a gate driving IC and a data driving IC are connected on an array substrate to simplify a FPC structure and a fabricating process. This method is referred to as a lines on glass (LOG) method.
FIG. 4 is a schematic plan view of an LCD device using an LOG method. Since the LCD device using an LOG method has the same structure as the conventional LCD device of FIG. 2 except LOG lines, illustrations for the same structure will be omitted.
In FIG. 4, a plurality of LOG lines 90 connecting a gate driving IC 81 and a data driving IC 82 are formed on an array substrate 50. Since the gate driving IC 81 and the data driving IC 82 are connected with the plurality of LOG lines 90 instead of a FPC, the fabricating process may be simplified and production cost may be reduced. In general, copper is used for the FPC because copper has very low resistivity among metallic materials. Accordingly, the plurality of LOG lines 90 should also have materials of low resistivity. Preferably, the plurality of LOG lines 90 are wide and short. Materials of low resistivity, for example, are aluminum (Al) or Al alloy. According to recent increase of display area, a gate line is made of Al or Al alloy to prevent a signal delay. Therefore, the plurality of LOG lines 90 may be formed through the same process as the gate line for reduction of fabricating steps and preserving low resistivity. However, since materials of Al or Al alloy are susceptible to chemicals such as etchant, it is preferable to form an additional metallic material such as molybdenum (Mo) on the Al or Al alloy.
On the other hand, since the plurality of LOG lines 90 are minimized in length to reduce resistance, the plurality of LOG lines 90 overlap the seal pattern 70. Therefore, a passivation layer (not shown) of organic insulating material should have grooves (not shown) between the plurality of LOG lines 90 to improve adhesion of the seal pattern 70.
FIG. 5A is a schematic magnified plan view of a portion xe2x80x9cDxe2x80x9d of FIG. 4, and FIG. 5B is a schematic cross-sectional view taken along a line Vbxe2x80x94Vb of FIG. 5A.
In FIGS. 5A and 5B, a plurality of LOG lines 90 of the same material as a gate line (not shown) are formed on an array substrate 50. The plurality of LOG lines 90 are spaced apart from each other. A gate insulating layer 56 and a passivation layer 57 of organic insulating material are sequentially formed on the plurality of LOG lines 90. The passivation layer 57 has grooves 57c between the adjacent LOG lines 90 and through the gate insulating layer 56. A seal pattern 70 is formed on the passivation layer 57. A color filter substrate 60 having a common electrode 61 is disposed over the seal pattern 70 and the seal pattern 70 attaches the color filter substrate 60 to the array substrate 50.
As mentioned above, a width of the LOG line 90 should be maximized to minimize its resistance. That is, the LOG line 90 is wider than the data link line (of FIGS. 3A and 3B). The width of the LOG line 90 is more than about twice the gap between the adjacent LOG lines 90. Accordingly, even though the passivation layer 57 under the seal pattern 70 between the adjacent LOG lines 90 is eliminated, the eliminated area is not large. As a result, an inferiority such as breakage of the seal pattern 70 may occur at a crossing portion of the plurality of LOG lines 90 and the seal pattern 70.
Accordingly, the present invention is directed to a liquid crystal display device that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide a liquid crystal display device using a line-on-glass (LOG) method where breakage of a seal pattern is prevented.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. Other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a liquid crystal display device includes: first and second substrates facing and spaced apart from each other; a seal pattern between the first and second substrates, the seal pattern defining a display region; gate and data lines formed on the first substrates at the display region, the gate and data lines crossing each other; gate and data driving ICs (integrated circuits) on the first substrate at an exterior of the display region, the gate and data driving ICs being connected to the gate and data lines, respectively; a LOG (line-on-glass) line on the first substrate, the LOG line connecting the gate and data driving ICs and overlapping the seal pattern; and a passivation layer covering the LOG line and having first and second grooves, the first groove being disposed between adjacent LOG lines, the second groove being disposed over the LOG line.
In another aspect, a liquid crystal display device includes: a first substrate having a display region and a non-display region; gate and data lines formed on the first substrates at the display region, the gate and data lines crossing each other; gate and data driving ICs (integrated circuits) on the first substrate at the non-display region, the gate and data driving ICs being connected to the gate and data lines, respectively; a LOG (line-on-glass) line on the first substrate at the non-display region, the LOG line connecting the gate and data driving ICs; a passivation layer covering the LOG line and having first and second grooves, the first groove being disposed between adjacent LOG lines, the second groove being disposed over the LOG line; a seal pattern on the passivation layer, the seal pattern covering the first and second grooves; and a second substrate on the seal pattern.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.